CY7C68013
Document #: 38-08012 Rev. *B
Page 4 of 50
LIST OF TABLES
Table 3-1. Special Function Registers ................................................................................................ 8
Table 3-2. Default ID Values for FX2 ................................................................................................... 8
Table 3-3. INT2 USB Interrupts ............................................................................................................ 9
Table 3-4. Individual FIFO/GPIF Interrupt Sources .......................................................................... 10
Table 3-5. Default Full-Speed Alternate Settings .............................................................................. 14
Table 3-6. Default High-Speed Alternate Settings ............................................................................ 15
Table 3-7. Strap Boot EEPROM Address Lines to These Values ................................................... 17
Table 4-1. FX2 Pin Descriptions ......................................................................................................... 23
Table 5-1. FX2 Register Summary ..................................................................................................... 30
Table 8-1. DC Characteristics ............................................................................................................ 36
Table 9-1. Program Memory Read Parameters ................................................................................ 37
Table 9-2. Data Memory Read Parameters ....................................................................................... 38
Table 9-3. Data Memory Write Parameters ....................................................................................... 39
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK ...................... 40
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK ..................... 40
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK ............... 41
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK ............... 41
Table 9-8. Slave FIFO Asynchronous Read Parameters .................................................................. 42
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK ............... 42
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK ............ 43
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ........... 43
Table 9-12. Slave FIFO Sync. Packet End Strobe Parameters with Internally Sourced IFCLK ... 43
Table 9-13. Slave FIFO Sync. Packet End Strobe Parameters with Externally Sourced IFCLK .. 44
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters ........................................ 44
Table 9-15. Slave FIFO Output Enable Parameters ......................................................................... 44
Table 9-16. Slave FIFO Address to Flags/Data Parameters ............................................................ 45
Table 9-17. Slave FIFO Synchronous Address Parameters ............................................................ 45
Table 9-18. Slave FIFO Asynchronous Address Parameters .......................................................... 45
Table 10-1. Ordering Information ...................................................................................................... 45
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