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ATXMEGA256A3 Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATXMEGA256A3 Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 76 page  8 8068E–AVR–08/08 XMEGA A3 7. Memories 7.1 Features • Flash Program Memory – One linear address space – In-System programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section for application code or bootloader code – Separate lock bits and protection for all sections • Data Memory – One linear address space – Single cycle access from CPU – SRAM – EEPROM Byte or page accessible Optional memory mapping for direct load and store – I/O Memory Configuration and Status register for all peripherals and modules 16-bit accessible General Purpose Register for global variables or flags – External Memory support – Bus arbitration Safe and deterministic handling of CPU and DMA Controller priority – Separate buses for SRAM, EEPROM, I/O Memory and External Memory access Simultaneous bus access for CPU and DMA Controller • Calibration Row Memory for factory programmed data Oscillator calibration bytes Serial number Device ID for each device type • User Signature Row One flash page in size Can be read and written from software Data is kept after Chip Erase 7.2 Overview The AVR architecture has two main memory spaces, the Program Memory and the Data Mem- ory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All three memory spaces are linear and require no paging. The available memory size configura- tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash memory signature row for calibration data, device identification, serial number etc. Non-volatile memory spaces can be locked for further write or read/write operations. This pre- vents unrestricted access to the application software. |
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