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PRELIMINARY

AT91SAM7A2 - Summary

6021BS–ATARM–06-Jul-04

be level sensitive or edge triggered. External sources can be programmed to be positive or

negative edge triggered or high or low level sensitive.

PIO: Parallel I/O

Controller

The AT91SAM7A2 has 57 configurable I/O lines. 32 pins (United PIO) on the AT91SAM7A2

are dedicated as general purpose I/O pins (UPIO0 to UPIO31). Other I/O lines are multiplexed

with an external signal of a peripheral to optimize the use of available package pins. The

United-PIO is controlled by a dedicated module. The others pins are configure in each module.

PDC: Peripheral

Data Controller

An on-chip, 10-channel Peripheral Data Controller (PDC) transfers data between the on-chip

peripherals and the on and off-chip memories without processor intervention. One PDC chan-

nel is connected to the receiving channel and one to the transmitting channel of each USART

and of the SPI. A single PDC channel is connected to each ADC and each Capture.

Most importantly, the PDC removes the processor interrupt handling over-head and signifi-

cantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64

Kbytes without reprogramming the starting address. As a result, the performance of the micro-

controller is increased and the power consumption reduced.

USART: Universal

Synchronous

Asynchronous

Receiver

Transmitter

The AT91SAM7A2 provides two identical, full-duplex, universal synchronous asynchronous

receiver transmitter which are connected to the Peripheral Data Controller. The main features

are:

•

Programmable Baud Rate Generator

•

Parity, Framing and Overrun Error Detection

•

Line Break Generation and Detection

•

Automatic Echo, Local & Remote Loopback Modes

•

Multi-drop Mode: Address Detection and Generation

•

Interrupt Generation

•

Two Dedicated Peripheral Data Controller Channels

•

5-, 6-, 7-, 8- and 9-bit Character Length

•

Idle Flag for J1587 Protocol.

•

Smart Card Transmission Error Feature

•

Support LIN 1.2 Protocol with H/W Layer

SPI: Serial

Peripheral

Interface

The AT91SAM7A2 features an SPI that provides communication with external devices in mas-

ter or slave mode. The SPI has four external chip selects that can be connected to up to 15

devices. The data length is programmable from 8- to 16-bit.

As for the USART, a two-channel PDC is used to move data directly between memory and the

SPI without CPU intervention for maximum real-time processing throughput.

CAN: Controller

Area Network

The AT91SAM7A2 provides four CANs (2.0A and 2.0B). These are based upon serial commu-

nications protocol which efficiently supports distributed real-time control with a very high level

of security (one with 32 mailboxes and the others with 16 mailboxes).

The main features are:

•

Prioritization of Messages

•Multi-master

•

System Wide Data Consistency

•

Error Detection and Error Signaling

•

Automatic Retransmission Of Corrupted Messages