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T89C51AC2-SLSC-M Datasheet(PDF) 7 Page - ATMEL Corporation |
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T89C51AC2-SLSC-M Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 117 page Draft.A - March 30, 2001 7 Preview - Confidential T89C51AC2 NOTE: 1. Port 0 is precluded from use as general purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain. Figure 2. Port 0 Structure NOTE: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cyle. Figure 3. Port 2 Structure When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output- driver input from the latch output to the internal address/data line. D Q P0.X LATCH INTERNAL WRITE TO LATCH READ PIN READ LATCH 0 1 P0.x (1) ADDRESS LOW/ DATA CONTROL VDD BUS (2) D Q P2.X LATCH INTERNAL WRITE TO LATCH READ PIN READ LATCH 0 1 P2.x (1) ADDRESS HIGH/ DATA CONTROL BUS VDD INTERNAL PULL-UP (2) |
Similar Part No. - T89C51AC2-SLSC-M |
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