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MAC7136 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MAC7136 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 710 page  Features MAC7100 Microcontroller Family Product Brief, Rev. 2 Preliminary Freescale Semiconductor 7 — Separately enabled transmitter and receiver — Separate receiver and transmitter CPU interrupt requests — Programmable transmitter output polarity — Two receiver wake-up methods — Interrupt-driven operation with eight flags — Receiver framing error detection — Hardware parity checking — 1/16-bit time noise reduction — Two DMA request lines per module (one each for receive and transmit data) — Support for LIN bus protocol (version 1.2 and version 2.0). – Full LIN master node autonomous message frame handling. – Frame hardware significantly reduces interrupt overhead. – LIN message header generation. – Slave timeout detection. – Optional CRC message checking. – Detection and flagging of LIN errors. • Inter-Integrated Circuit (I2C) Bus module — Two wire bi-directional serial bus for on-board communications — Compatibility with I2C Bus standard — Multi-master operation — Software-programmable for one of 256 different serial clock frequencies — Interrupt-driven byte-by-byte data transfer — Arbitration-lost interrupt with automatic mode switching from master to slave — Calling address identification interrupt — Start and stop signal generation/detection — Repeated START signal generation — Acknowledge bit generation/detection — Bus-busy detection — Two DMA request lines to receive and transmit data • Periodic Interrupt Timer (PIT) Module — Independent timeout periods for each of the ten 24-bit timers — One real-time interrupt (RTI) timer to wake up the CPU in wait mode or pseudo-stop mode — Eight timers that can be configured to generate DMA trigger pulses — Four timers that can be configured to generate interrupts instead of triggers — Two timers that can be configured to generate ATD trigger pulses • Miscellaneous Control Module (MCM) — Program-visible information regarding the device configuration and revision — SPP module configuration and reset status — Software watchdog timer with programmable, staged response — Wake-up control for exiting sleep modes — Cross-bar switch remapping — Address information for faulted memory accesses |
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