MAC7100 Microcontroller Family Product Brief, Rev. 2

Preliminary

Functional Overview

Freescale Semiconductor

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4.2

Enhanced Direct Memory Access (eDMA) and

Channel Multiplexer (DMA MUX)

The implementation of the eDMA on the MAC7100 family is targeted towards cost-sensitive applications

while providing a high level of functionality. The eDMA executes in parallel with the CPU, which enables

transfers of data between the memory, peripherals, and off-chip devices with little intervention from the

core; thus increasing system performance as well as simplifying software development. The eDMA is

capable of performing complex data transfers with minimal intervention from a host processor via 16

programmable DMA channels. The hardware microarchitecture includes the eDMA engine (which

performs source / destination address calculations and data movement operations), and a dedicated

memory array containing transfer control descriptors. The SRAM-based implementation is utilized to

minimize overall module size.

4.3

External Interface Module (EIM)

The EIM connects the device to off-chip resources and is not available in all MAC7100 packages. Two

components make up this module: a user-programmable chip select module and the bus controller. The bus

controller uses a simple, flexible bus protocol that supports a variety of external memory devices with little

or no external logic needed, and is based on the external bus of the 68K/Coldfire® family of devices. All

transfers on the external bus are controlled by the MCU masters (CPU or eDMA).

The EIM supports a normal three clock-cycle access, but a two cycle fast termination can also be used if

the transfer acknowledge signal is asserted before the rising edge of the second CLKOUT cycle. The EIM

also provides support for burst transfers of up to 16 bytes of data with the proper external support logic.

4.4

Common Flash Module (CFM)

The CFM provides up to 1 Mbyte of 32-bit program Flash memory and 32 Kbytes of 16-bit data Flash

memory. The Flash memory serves as electrically erasable and programmable, non-volatile memory. It is

ideal for program and data storage for single-chip applications allowing for field reprogramming without

requiring external programming voltage sources. For more information on the non-volatile memory

options on MAC7100 devices, refer to Table 1.

4.5

Interrupt Controller (INTC)

MAC7100 family devices implement an Interrupt Controller (INTC) Module which supports 64 interrupt

requests. The INTC is a highly-programmable controller, collecting interrupt requests, mapping the

requests into 16 priority levels, and then signalling the ARM processor when a properly enabled unmasked

request is active. In response to the service routine’s memory mapped interrupt acknowledge read cycle,

the INTC returns a unique vector for each interrupt request and automatically manages masking of lower

level requests. As any interrupt source can be assigned to any of the sixteen priority levels, and the INTC

enables the definition of which priority levels are assigned to fast or normal interrupts, each interrupt

source can be selected to generate either a fast or normal interrupt to the core by its assigned level.