DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers

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Note 1:

Specifications to -40∞C are guaranteed by design and not production tested.

Note 2:

All voltages are referenced to ground.

Note 3:

the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper

operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset.

Note 4:

given, there is guaranteed separation between these two voltages.

Note 5:

Note 6:

disconnected.

Note 7:

Note 8:

RST = 5.5V. This condition mimics the operation of pins in I/O mode.

Note 9:

During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition

mode.

Note 10:

When addressing external memory.

Note 11:

Guaranteed by design.

Note 12:

Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V.

Note 13:

RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode.

Note 14:

This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at

approximately 2V.