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T87C5112-RKUIL Datasheet(PDF) 11 Page - ATMEL Corporation |
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T87C5112-RKUIL Datasheet(HTML) 11 Page - ATMEL Corporation |
11 / 97 page Rev. B - November 10, 2000 11 Preliminary T80C5112 · A software instruction which set X2 bit desactivates the precaler/divider, so the internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit. 6.5. Timer 0 : Clock Inputs Figure 2. Timer 0 : Clock Inputs The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allow to perform a Real Time Clock function. SCLKT0=0: Timer 0 uses the standard T0 pin as clock input ( Standard mode ) SCLKT0=1: Timer 0 uses the special Sub Clock as clock input. When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0. With a 32 kHz crystal, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real Time Clock (RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 KHz most of the time. When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others peripherals. 6.6. Registers 6.6.1. Configuration byte The configuration byte is a special register. Its content is defined by the diffusion mask in the ROM version or is rerad or written by the OTP programmer in the OTP version. This register can also be accessed as a read only register. CONF - Configuration byte (EFh) 7 6 5 4 3 2 1 0 LB1 LB2 LB3 RST_OSC XT_SP RST_EXT OSCC_OFF Bit Number Bit Mnemonic Description 7:5 - Program memory lock bits See chapter program memory for the deÞnition of these bits.. SCLKT0 1 0 CkIdle :6 T0 pin Sub Clock C/T 1 0 OSCCON TMOD Gate INT0 TR0 Timer 0 Control |
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