Page 11
Page 10
*See NOTE on previous page.
SERIAL CHANNEL SELECTION TABLE
CHANNEL
TX FREQUENCY
RX LO
CHANNEL
TX FREQUENCY
RX LO
0
902.62
867.92
51
915.37
880.67
1
902.87
868.17
52
915.62
880.92
2
903.12
868.42
53
915.87
881.17
3
903.37
868.67
54
916.12
881.42
4
903.62
868.92
55
916.37
881.67
5
903.87
869.17
56
916.62
881.92
6
904.12
869.42
57
916.87
882.17
7
904.37
869.67
58
917.12
882.42
8
904.62
869.92
59
917.37
882.67
9
904.87
870.17
60
917.62
882.92
10
905.12
870.42
61
917.87
883.17
11
905.37
870.67
62
918.12
883.42
12
905.62
870.92
63
918.37
883.67
13
905.87
871.17
64
918.62
883.92
14
906.12
871.42
65
918.87
884.17
15
906.37
871.67
66
919.12
884.42
16
906.62
871.92
67
919.37
884.67
17
906.87
872.17
68
919.62
884.92
18
907.12
872.42
69
919.87
885.17
19
907.37
872.67
70
920.12
885.42
20
907.62
872.92
71
920.37
885.67
21
907.87
873.17
72
920.62
885.92
22
908.12
873.42
73
920.87
886.17
23
908.37
873.67
74
921.12
886.42
24
908.62
873.92
75
921.37
886.67
25
908.87
874.17
76
921.62
886.92
26
909.12
874.42
77
921.87
887.17
27
909.37
874.67
78
922.12
887.42
28
909.62
874.92
79
922.37
887.67
29
909.87
875.17
80
922.62
887.92
30
910.12
875.42
81
922.87
888.17
31
910.37
875.67
82
923.12
888.42
32
910.62
875.92
83
923.37
888.67
33
910.87
876.17
84
923.62
888.92
34
911.12
876.42
85
923.87
889.17
35
911.37
876.67
86
924.12
889.42
36
911.62
876.92
87
924.37
889.67
37
911.87
877.17
88
924.62
889.92
38
912.12
877.42
89
924.87
890.17
39
912.37
877.67
90
925.12
890.42
40
912.62
877.92
91
925.37
890.67
41
912.87
878.17
92
925.62
890.92
42
913.12
878.42
93
925.87
891.17
43
913.37
878.67
94
926.12
891.42
44
913.62
878.92
95
926.37
891.67
45
913.87
879.17
96
926.62
891.92
46
914.12
879.42
97
926.87
892.17
47
914.37
879.67
98
927.12
892.42
48
914.62
879.92
99
927.37
892.67
49
914.87
880.17
100
927.62
892.92
50*
915.12
880.42
= Also available in Parallel Mode
CHANNEL SELECTION
Parallel Selection
All HP3 receiver models feature eight
parallel selectable channels. Parallel
Mode is selected by grounding the
MODE line. In this mode, channel
selection is determined by the logic
states of pins CS0, CS1, and CS2, as
shown in the adjacent table. A ‘0’
represents ground and a ‘1’ the positive supply. The on-board microprocessor
performs all PLL loading functions, eliminating external programming and
allowing channel selection via DIP switches or a product’s processor.
Serial Selection
In addition to the Parallel Mode, PS versions of the HP3 also feature 100 serially
selectable channels. The Serial Mode is entered when the MODE line is left open
or held high. In this condition, CS1 and CS2 become a synchronous serial port,
with CS1 serving as the clock line and CS2 as the data line. The module is easily
programmed by sending and latching the binary number (0 to 100) of the desired
channel (see the adjacent Serial Channel Selection Table). With no additional
effort, the module’s microprocessor handles the complex PLL loading functions.
The
Serial
Mode
is
straightforward; however,
minimum timings and bit
order must be followed.
Loading is initiated by
taking the clock line high
and the data line low as
shown.
The
eight-bit
channel number is then
clocked-in one bit at a
time, with the LSB first.
There is no maximum time for this process, only the minimum times that must be
observed. After the eighth bit, both the clock and data lines should be taken high
to trigger the automatic data latch. A typical software routine can complete the
loading sequence in under 200uS. Sample code is available on the Linx website.
NOTE: When the module is powered up in the Serial Mode, it will default to channel 50 until changed
by user software. This allows testing apart from external programming and prevents out-of-band
operation. When programmed properly, the dwell time on this default channel can be less than 200uS.
Channel 50 is not counted as a usable channel since data errors may occur as transmitters also default
to channel 50 on startup. If a loading error occurs, such as a channel number >100 or a timing problem,
the receiver will default to serial channel 0. This is useful for debugging as it verifies serial port activity.
Table 2: Parallel Channel Selection Table
Variable Data
Note 3
Note 2
Note 1
12345678
T1
25µs
T2
5µs
T3
8µs
T4
5µs
Data
Clock
T0
1ms
(T0) Time between packets or prior to data startup ................................1mS min.
(T1) Data-LO / Clock-HI to Data-LO / Clock-LO .......................................25µS min.
(T2) Clock-LO to Clock-HI ...........................................................................5µS min.
(T3) Clock-HI to Clock-LO ...........................................................................8µS min.
(T4) Data-HI / Clock-HI .................................................................................5µS min.
Total Packet Time ......................................................................................157µS min.
1) Loading begins when clock line is high and data line is taken low
2) Ensure that edge is fully risen prior to high-clock transition
3) Both lines high triggers automatic latch
Figure 13: PLL Serial Data Timing
CS2
CS1
CS0
Channel
Frequency
0
0
0
0
903.37
0
0
1
1
906.37
0
1
0
2
907.87
0
1
1
3
909.37
1
0
0
4
912.37
1
0
1
5
915.37
1
1
0
6
919.87
1
1
1
7
921.37
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
