STLC5048 datasheet(7/45 Pages) STMICROELECTRONICS

Part #	STLC5048

Description	FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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STLC5048

FUNCTIONAL DESCRIPTION

The STLC5048 is a fully programmable device with embedded ROM and RAM. The ROM is used to contain the default

state coefficients for the programmable filters, while the RAM is used to load the desired coefficient values.

POWER ON INITIALIZATION

When power is first applied it is recommended to reset the device (M1=M0=0) in order to set all the internal reg-

isters to the reset value (see register description); this means also power down mode for all the four channels

and SW reset bit (RES) set in the CONF register.

When the RES bit is set, the only instructions allowed are the one that disable this bit and the REACOM instruc-

tion: all other instructions are ignored. It is not possible to disable the RES bit and write the other bits of the

CONF register with the same instruction.

Of course, RESET mode can be programmed also by writing the RES bit of the CONF register.

See appendix C for the power up sequence.

During RESET condition all the I/On and CSn pins are set as inputs, DX is in high impedance and all VFROn

are set to AGND. After the reset all registers are loaded with the reset value.

It means that the PCM interface and all the VFRO outputs are configured as described in the Power Down State,

while no transmit or receive time slot are set.

Then, filters and gain blocks are configured with the coefficient defined in the Default State.

POWER DOWN STATE

Each of the four channel may be put into power down mode by setting the appropriate bit in the CONF register.

In this mode the eventual programmed DX channel is set in high impedance while the VFRO outputs are forced

to AGND. When all the channels are set in Power Down mode the device enters the Power Down state: all the

blocks related to the data processing are turned off, while the RAM is On or Off according to the PDR bit value

in the COMEN register.

Figure 1. Block Diagram of a single channel.

A/mu

DR

VFRO

VFXI

HPR

R

GR

B

Z

KD

KA

**

*

**

*

LPR

D/A

RX

TX

A/mu

DX

HPX

X

GX

**

* PROGRAMMABLE BLOCKS

D00TL468

LPX

A/D

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