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STLC7550TQFP Datasheet(PDF) 7 Page - STMicroelectronics |
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STLC7550TQFP Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 17 page Bit 3-4-5 Internal Sampling M/S Sync FS SCLK (OCLK) % OVER XTALIN (MCLK) XTALOUT ÷ M ÷ Q MCM Cont. Reg. : Bit 8-9-10-11-12-13 V DD Figure 1 : Clock Block Diagram FUNCTIONAL DESCRIPTION (continued) 4 - MODES OF OPERATION Thanks to MCM and M/S programmation pins we can get the following configuration. Configuration 1 : MCM = 1, M/S = 1 The STLC7550 is in master mode and we have : Fs = XTAL IN / (M x Q x OVER) Fs and SCLK are output pins. SCLK FS DIN DOUT BCLK FS DO DI XTALIN M/S MCM STLC7550 PROCESSOR V DD f Q = 36.864MHz V DD TS GND Figure 2 : Configuration 1 SCLK FS DIN DOUT XTALIN M/S MCM STLC7550 V DD GND f Q = K x Fs BCLK FS DO DI PROCESSOR TS GND Figure 4 : Configuration 3 (7546 mode) SCLK FS DIN DOUT BCLK FS DO DI XTALIN M/S MCM STLC7550 PROCESSOR GND V DD f Q = 36.864MHz TS GND Figure 3 : Configuration 2 Configuration 2 : MCM = 1, M/S = 0 The STLC7550 is in slave mode. SCLK is provided by the STLC7550, the processor generates the Fs and controls the phase of the sampling frequency. Fs must be the result of a division of a number of cycles of SLCK (Fs = SCLK % OVER). Configuration 3 : MCM = 0, M/S = 1 The STLC7550 is in master mode and the proces- sor provides the XTAL IN = MCLK = OCLK. The STLC7550 generates the Fs from OCLK. In this mode the configuration 3 is equivalent to the STLC7546 mode. Configuration 4 : MCM = 0, M/S = 0 The STLC7550 is in slave mode. The configuration 4 is equivalent to configuration 3 but the Fs is generated and phase controlled by the processor. Configuration 5 : MCM = 1, M/S = 1 (master codec) MCM = 0, M/S = 0 (slave codec) This is dual codec application. The master codec has his data in timeslot 0 and the slave codec has his data in timeslot 1 thanks to the programmation of TS. STLC7550 7/17 |
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