1.
General description
The LPC1766 is an ARM Cortex-M3 based microcontroller for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC1766 operates at CPU frequencies of up to 80 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1766 includes 256 kB of flash memory, 64 kB of
data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general
purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3
I2C interfaces, 2-input plus 2-output I2S interface, 8 channel 12-bit ADC, 10-bit DAC,
motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output
general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70
general purpose I/O pins.
The LPC1766 is pin-compatible to the LPC2366 ARM7-based microcontroller.
2.
Features
ARM Cortex-M3 processor, running at frequencies of up to 80 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
256 kB on-chip flash programmimg memory. Enhanced flash memory accelerator
enables high-speed 80 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot
loader software.
64 kB on-chip SRAM includes:
32 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
Two 16 kB SRAM blocks with separate access paths for higher throughput. These
SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for
general purpose CPU instruction and data storage.
LPC1766
32-bit ARM Cortex-M3 microcontroller; 256 kB flash and 64 kB
SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN, 12-bit
ADC, and 10-bit DAC
Rev. 00.02 — 12 August 2008
Objective data sheet
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