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V61C518256-15R Datasheet(PDF) 1 Page - Mosel Vitelic, Corp |
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V61C518256-15R Datasheet(HTML) 1 Page - Mosel Vitelic, Corp |
1 / 12 page MOSEL VITELIC 1 V61C518256 32K X 8 HIGH SPEED STATIC RAM PRELIMINARY V61C518256 Rev. 0.3 July 1998 Features s High-speed: 10, 12, 15 ns s Low Power Dissipation: – CMOS Standby: 0.5 mA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages – 28-pin TSOP (Standard) – 28-pin 300 mil SOJ Description The V61C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three- state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Temperature Mark T N R 101215 0 °C to 70 °C •••••• Blank Functional Block Diagram Row Decoder 512 x 512 Memory Array Input Data Circuit Column I/O Column Decoder Control Circuit VCC GND A0 A1 A6 A10 518256-01 A13 A14 I/O0 I/O7 CE OE WE A2 A12 A11 A5 |
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