USBLC6-2P6 datasheet(4/14 Pages) STMICROELECTRONICS

Part #	USBLC6-2P6

Description	Very low capacitance ESD protection

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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Technical information

USBLC6-2

4/14

2

Technical information

2.1

Surge protection

The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail

topology.

The clamping voltage VCL can be calculated as follow :

VCL+ = VTRANSIL + VF for positive surges

VCL- = - VF for negative surges

with: VF = VT + Rd.Ip

(VF forward drop voltage) / (VT forward drop threshold voltage)

and VTRANSIL = VBR + Rd_TRANSIL.IP

Calculation example

We assume that the value of the dynamic resistance of the clamping diode is typically:

Rd = 0.5 Ω and VT = 1.1 V

We assume that the value of the dynamic resistance of the transil diode is typically:

Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V

For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 Ω),

VBUS = +5 V, and if in first approximation, we assume that :

Ip = Vg / Rg = 24 A.

So, we find:

VCL+ = +31.2 V

VCL- = -13 V

Note:

The calculations do not take into account phenomena due to parasitic inductances.

2.2

Surge protection application example

If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from

GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume

that the parasitic inductances LVBUS, LI/O and LGND of these tracks are about 6 nH. So when

an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (tr=1ns), the

voltage VCL has an extra value equal to LI/O.dl/dt+LGND.dI/dt.

The dI/dt is calculated as:

dI/dt = Ip/tr = 24 A/ns

The overvoltage due to the parasitic inductances is:

LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the

clamping voltage will be :

VCL+ = +31.2 + 144 + 144 = 319.2 V

VCL- = -13.1 - 144 - 144 = -301.1 V

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