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74VHCT125A Datasheet(PDF) 1 Page - STMicroelectronics

Part No. 74VHCT125A
Description  QUAD BUS BUFFERS (3-STATE)
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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1/12
December 2004
s
HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V
s
LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA=25°C
s
COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN.), VIL = 0.8V (MAX)
s
POWER DOWN PROTECTION ON INPUTS
& OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: VOLP = 0.8V (MAX.)
DESCRIPTION
The 74VHCT125A is an advanced high-speed
CMOS QUAD BUS BUFFERS fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V since all
inputs are equipped with TTL threshold.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHCT125A
QUAD BUS BUFFERS (3-STATE)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74VHCT125AMTR
TSSOP
74VHCT125ATTR
TSSOP
SOP
Rev. 6




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