10
General-Purpose Timers ................................................................................................. 195
10.1
Block Diagram ........................................................................................................................ 196
10.2
Functional Description ............................................................................................................. 196
10.2.1 GPTM Reset Conditions .......................................................................................................... 196
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 196
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 198
10.3
Initialization and Configuration ................................................................................................. 202
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 202
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 203
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 203
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 204
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 204
10.3.6 16-Bit PWM Mode ................................................................................................................... 205
10.4
Register Map .......................................................................................................................... 205
10.5
Register Descriptions .............................................................................................................. 206
11
Watchdog Timer ............................................................................................................... 231
11.1
Block Diagram ........................................................................................................................ 231
11.2
Functional Description ............................................................................................................. 231
11.3
Initialization and Configuration ................................................................................................. 232
11.4
Register Map .......................................................................................................................... 232
11.5
Register Descriptions .............................................................................................................. 233
12
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 254
12.1
Block Diagram ........................................................................................................................ 255
12.2
Functional Description ............................................................................................................. 255
12.2.1 Transmit/Receive Logic ........................................................................................................... 255
12.2.2 Baud-Rate Generation ............................................................................................................. 256
12.2.3 Data Transmission .................................................................................................................. 257
12.2.4 Serial IR (SIR) ......................................................................................................................... 257
12.2.5 FIFO Operation ....................................................................................................................... 258
12.2.6 Interrupts ................................................................................................................................ 258
12.2.7 Loopback Operation ................................................................................................................ 259
12.2.8 IrDA SIR block ........................................................................................................................ 259
12.3
Initialization and Configuration ................................................................................................. 259
12.4
Register Map .......................................................................................................................... 260
12.5
Register Descriptions .............................................................................................................. 261
13
Synchronous Serial Interface (SSI) ................................................................................ 295
13.1
Block Diagram ........................................................................................................................ 295
13.2
Functional Description ............................................................................................................. 295
13.2.1 Bit Rate Generation ................................................................................................................. 296
13.2.2 FIFO Operation ....................................................................................................................... 296
13.2.3 Interrupts ................................................................................................................................ 296
13.2.4 Frame Formats ....................................................................................................................... 297
13.3
Initialization and Configuration ................................................................................................. 304
13.4
Register Map .......................................................................................................................... 305
13.5
Register Descriptions .............................................................................................................. 306
14
Inter-Integrated Circuit (I2C) Interface ............................................................................ 332
14.1
Block Diagram ........................................................................................................................ 332
5
October 09, 2007
Preliminary
LM3S6611 Microcontroller