M48T35 M48T35Y

Operation modes

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2.3

Data retention mode

Should the supply voltage decay, the RAM will automatically power-fail deselect, write

become high impedance, and all inputs are treated as “Don't care” (see Figure 12 on

page 19, Table 10, and Table 11 on page 20).

Note:

A power failure during a WRITE cycle may corrupt data at the currently addressed location,

of the power supply lines is recommended.

preserves data and powers the clock. The internal button cell will maintain data in the

For more information on Battery Storage Life refer to the Application Note AN1012.

WRITE Enable Pulse Width

50

ns

Chip Enable Low to Chip Enable High

55

ns

WRITE Enable High to Address Transition

0

ns

Chip Enable High to Address Transition

0

ns

Input Valid to WRITE Enable High

30

ns

Input Valid to Chip Enable High

30

ns

WRITE Enable High to Input Transition

5

ns

Chip Enable High to Input Transition

5

ns

(2)(3)

WRITE Enable Low to Output Hi-Z

25

ns

Address Valid to WRITE Enable High

60

ns

Address Valid to Chip Enable High

60

ns

(2)(3)

WRITE Enable High to Output Transition

5

ns

1.

noted).

2.

3.

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Table 4.

Write mode AC characteristics (continued)

Symbol

M48T35/Y

Unit

Min

Max