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STM817 Datasheet(PDF) 10 Page - STMicroelectronics |
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STM817 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 37 page STM690A/692A/703/704/802/805/817/818/819 10/37 Back-up Battery Switchover In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the back-up supply when VCC falls. Note: If back-up battery is not used, connect both VBAT and VOUT to VCC. This family of Supervisors does not always con- nect VBAT to VOUT when VBAT is greater than VCC. VBAT connects to VOUT (through a 100Ω switch) when VCC is below VRST and VBAT. This is done to allow the back-up battery (e.g., a 3.6V lithium cell) to have a higher voltage than VCC. Assuming VBAT > 2.0V, switchover at VSO ensures that battery back-up mode is entered before VOUT gets too close to the 2.0V minimum required to re- liably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscilla- tion around the VSO point. VOUT is connected to VCC through a 3Ω PMOS power switch. Note: The back-up battery may be removed while VCC is valid, assuming VBAT is adequately decou- pled (0.1µF typ), without danger of triggering a re- set. Table 4. I/O Status in Battery Back-up Chip-Enable Gating (STM818 only) Internal gating of the chip enable (E) signal pre- vents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage con- dition. The STM818 uses a series transmission gate from E to ECON (see Figure 12., page 11). During normal operation (reset not asserted), the E transmission gate is enabled and passes all E transitions. When reset is asserted, this path be- comes disabled, preventing erroneous data from corrupting the CMOS RAM. The short E propaga- tion delay from E to ECON enables the STM818 to be used with most µPs. If E is low when reset as- serts, ECON remains low for typically 15µs to per- mit the current WRITE cycle to complete. Connect E to VSS if unused. Chip Enable Input (STM818 only) The chip-enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the chip-enable transmission gate disables and E immediately be- comes high impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable transmission gate will disable 15µs after reset as- serts (see Figure 13., page 11). This permits the current WRITE cycle to complete during power- down. Any time a reset is generated, the chip-enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the reset time-out period. When the chip enable trans- mission gate is enabled, the impedance of E ap- pears as a 40 Ω resistor in series with the load at ECON. The propagation delay through the chip-en- able transmission gate depends on VCC, the source impedance of the drive connected to E, and the loading on ECON. The chip enable propa- gation delay is production tested from the 50% point on E to the 50% point on ECON using a 50Ω driver and a 50pF load capacitance (see Figure 40., page 28). For minimum propagation delay, minimize the capacitive load at ECON and use a low-output impedance driver. Chip Enable Output (STM818 only) When the chip-enable transmission gate is en- abled, the impedance of ECON is equivalent to a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission gate is off and an active pull-up connects ECON to VOUT (see Figure 12., page 11). This pull-up turns off when the transmission gate is enabled. Pin Status VOUT Connected to VBAT through internal switch VCC Disconnected from VOUT PFI Disabled PFO Logic low E High impedance ECON Logic high WDI Watchdog timer is disabled WDO Logic low MR Disabled RST Logic low RST Logic high VBAT Connected to VOUT |
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