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TDA7463AD Datasheet(PDF) 4 Page - STMicroelectronics |
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TDA7463AD Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 13 page TDA7463AD 4/13 3I2C BUS INTERFACE Data transmission from microprocessor to the TDA7463AD and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig.5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master ( µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 6). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 4. Data Validity on the I2CBUS Figure 5. Timing Diagram of I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 SCL SDA START I2CBUS STOP D99AU1032 |
Similar Part No. - TDA7463AD_05 |
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Similar Description - TDA7463AD_05 |
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