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AMIS-30522ANA Datasheet(PDF) 6 Page - AMI SEMICONDUCTOR

Part # AMIS-30522ANA
Description  Micro-stepping Motor Driver
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Manufacturer  AMI [AMI SEMICONDUCTOR]
Direct Link  http://www.amis.com
Logo AMI - AMI SEMICONDUCTOR

AMIS-30522ANA Datasheet(HTML) 6 Page - AMI SEMICONDUCTOR

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AMIS-30522 Micro-stepping Motor Driver
Data Sheet
6.4 AC Parameters
The AC parameters are given for VBB and temperature in their operating ranges.
Table 6: AC Parameters
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min.
Typ.
Max.
Unit
Internal Oscillator
fosc
Frequency of internal oscillator
3.6
4
4.4
MHz
Motordriver
PWM frequency
20.8
22.8
24.8
kHz
fPWM
Double PWM frequency
Frequency depends only on
internal oscillator
41.6
45.6
49.6
kHz
fj
PWM jitter frequency
tbd
Hz
fd
MOTxx
PWM jitter Depth
tbd
% fPWM
EMC[1:0] = 00
150
V/µs
EMC[1:0] = 01
100
V/µs
EMC[1:0] = 10
50
V/µs
Tbrise
MOTxx
Turn-on voltage slope, 10% to 90%
EMC[1:0] = 11
25
V/µs
EMC[1:0] = 00
150
V/µs
EMC[1:0] = 01
100
V/µs
EMC[1:0] = 10
50
V/µs
Tbfall
MOTxx
Turn-off voltage slope, 90% to 10%
EMC[1:0] = 11
25
V/µs
Digital Outputs
TH2L
DO
ERRB
Output fall-time from VinH to VinL
Capacitive load 400pF and pull-
up resistor of 1.5 k
50
ns
Charge Pump
fCP
CPN CPP Charge pump frequency
250
kHz
TCPU
MOTxx Start-up time of charge pump
Spec external components
CLR Function
TCLR
CLR
Hard reset duration time
20
90
µs
Power-Up
tPU
Power-up time
VBB=12V, ILOAD=50mA,
CLOAD=220nF
110
µs
tPD
Power-down time
External conditions tbd
ms
tPOR
Reset duration
100
ms
tRF
PORB/
WD
Reset filter time
1
µs
Watchdog
tWDTO
Watchdog time out interval
32
512
ms
tWDPR
Prohibited watchdog acknowledge delay
2
ms
tWDRD
PORB/
WD
Watchdog reset delay
tbd
µs
6.5 SPI Timing
Table 7: SPI Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
tCLK
SPI clock period
1
µs
tCLK_HIGH
SPI clock high time
100
ns
tCLK_LOW
SPI clock low time
100
ns
tSET_DI
DI set up time, valid data before rising edge of CLK
50
ns
tHOLD_DI
DI hold time, hold data after rising edge of CLK
50
ns
tCSB_HIGH
CSB high time
2.5
µs
tSET_CSB
CSB set up time, CSB low before rising edge of CLK
100
ns
tSET_CLK
CLK set up time, CLK low before rising edge of CSB
100
ns
6
AMI Semiconductor
– June 2007, M-20684-001
www.amis.com


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