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GAL20V8C-5LJ Datasheet(PDF) 9 Page - Lattice Semiconductor |
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GAL20V8C-5LJ Datasheet(HTML) 9 Page - Lattice Semiconductor |
9 / 25 page Specifications GAL20V8 9 Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 18 & 19 can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 18 & 19 are permanently configured to this function. Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 18 & 19 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. In the Simple mode, pins are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 14L8 and 16P6 devices with many permutations of ge- neric output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has pro- grammable polarity. Pins 1 and 13 are always available as data inputs into the AND array. The “center” two macrocells (pins 18 and 19) cannot be used in the input configuration. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Vcc XOR Vcc XOR Simple Mode |
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