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ISPLSI1032E125LJI Datasheet(PDF) 9 Page - Lattice Semiconductor |
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ISPLSI1032E125LJI Datasheet(HTML) 9 Page - Lattice Semiconductor |
9 / 17 page 9 Specifications ispLSI 1032E Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037A/1032E Outputs UNITS -100 MIN. MIN. MAX. MAX. DESCRIPTION # PARAM. 49 Output Buffer Delay ns toen 51 I/O Cell OE to Output Enabled ns tgy0 54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) ns Global Reset Clocks tgr 59 Global Reset to GLB and I/O Registers ns todis 52 I/O Cell OE to Output Disabled ns tgy1/2 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line ns tgcp 56 Clk Delay, Clock GLB to Global GLB Clk Line ns tioy2/3 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line ns tiocp 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line ns tgoe 53 Global OE ns tsl 50 Output Buffer Delay, Slew Limited Adder ns -125 – – 1.5 – 1.5 0.8 0.0 0.8 – – – 2.0 5.1 1.5 4.3 5.1 1.5 1.8 0.0 1.8 3.9 10.0 – – 1.4 – 1.4 0.8 0.0 0.8 – – – 1.3 4.3 1.4 2.8 4.3 1.4 1.8 0.0 1.8 2.7 9.9 |
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