7

Specifications ispLSI 1016E

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

Table 2-0037-16/125,100,80

Outputs

UNITS

-125

MIN.

-100

MIN.

MAX.

MAX.

DESCRIPTION

#

2

PARAMETER

49 Output Buffer Delay

–

–

1.7

ns

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

1.3

1.4

1.4

ns

Global Reset

1.4

50 Output Slew Limited Delay Adder

–

–

10.0

ns

10.0

51 I/O Cell OE to Output Enabled

–

–

5.3

ns

4.3

Clocks

1.3

59 Global Reset to GLB and I/O Registers

–

–

5.5

ns

3.2

52 I/O Cell OE to Output Disabled

–

–

5.3

ns

4.3

53 Global Output Enable

–

–

3.7

ns

2.7

55 Clock Delay, Y1 or Y2 to Global GLB Clock Line

2.3

2.4

2.9

ns

2.7

56 Clock Delay, Clock GLB to Global GLB Clock Line

0.8

0.8

1.8

ns

1.8

57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line

0.0

0.0

0.4

ns

0.3

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

0.8

0.8

1.8

ns

1.8

-80

MIN. MAX.

–

–

3.0

–

10.0

–

6.4

–

6.4

–

4.1

4.5

2.1

2.1

3.6

4.4

1.2

2.7

0.0

0.6

1.2

2.7