Specifications ispLSI 2192VE

7

Over Recommended Operating Conditions

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036E/2192VE v0.1

Inputs

UNITS

-225

MIN. MAX.

DESCRIPTION

#

2

PARAMETER

20 Input Buffer Delay

ns

21 Dedicated Input Delay

ns

22 GRP Delay

ns

GLB

25 1 Product Term/XOR Path Delay

ns

26 20 Product Term/XOR Path Delay

ns

27 XOR Adjacent Path Delay

ns

28 GLB Register Bypass Delay

ns

29 GLB Register Setup Time before Clock

ns

30 GLB Register Hold Time after Clock

ns

31 GLB Register Clock to Output Delay

ns

3

32 GLB Register Reset to Output Delay

ns

33 GLB Product Term Reset to Register Delay

ns

34 GLB Product Term Output Enable to I/O Cell Delay

ns

35 GLB Product Term Clock Delay

ns

ORP

38 Output Buffer Delay

ns

39 Output Slew Limited Delay Adder

ns

GRP

23 4 Product Term Bypass Path Delay (Combinatorial)

ns

24 4 Product Term Bypass Path Delay (Registered)

ns

36 ORP Delay

ns

37 ORP Bypass Delay

ns

Outputs

40 I/O Cell OE to Output Enabled

ns

41 I/O Cell OE to Output Disabled

ns

42 Global Output Enable

ns

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

ns

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line

ns

Clocks

45 Global Reset to GLB

0.3

0.5

0.2

3.2

3.2

3.2

0.0

–

–

0.3

0.3

4.0

2.9

3.2

1.6

2.0

1.5

2.2

0.9

0.4

2.6

2.6

1.9

0.9

1.1

3.7

–

–

–

–

–

–

–

0.7

1.8

–

–

–

–

0.8

–

–

–

–

–

–

–

–

–

0.9

1.1

–ns

Global Reset

-180

MIN. MAX.

0.5

1.1

0.6

3.4

3.4

3.4

0.0

–

–

0.3

0.6

4.3

5.9

4.0

1.6

2.0

1.9

2.4

1.4

0.4

3.0

3.0

2.0

1.2

1.4

4.4

–

–

–

–

–

–

–

1.2

2.3

–

–

–

–

1.0

–

–

–

–

–

–

–

–

–

1.2

1.4

–