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ISPPAC-POWR1208P1 Datasheet(PDF) 6 Page - Lattice Semiconductor |
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ISPPAC-POWR1208P1 Datasheet(HTML) 6 Page - Lattice Semiconductor |
6 / 34 page Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet 3-6 High Voltage FET Drivers Power-On-Reset Symbol Parameter Conditions Min. Typ. Max. Units VPP Range Programmable gate driver voltage (eight steps) (Note 1) 8 — 12 V VPP Accuracy Absolute accuracy of VPP output voltage 25°C -10 — 10 % VPP Step Gate driver voltage step (Note 2) — 0.5 — V ISOURCE Range Programmable ISOURCE current (32 steps) 0.5 — 50 µA ISOURCE Accuracy Absolute accuracy of ISOURCE current —10— % ISTEP Relative current value, from any ISOURCE setting to the next —15— % RSINK Gate driver sink/discharge resistor when setting FET driver to a LOW state FET Driver in OFF state —8— kΩ 1. Maximum voltage of VPP is not to exceed 7.5V over VDD. 2. The high voltage driver outputs are set in software, HVOUT voltage range is between 8V and 12V. VDD values determine the maximum VPP. Symbol Parameter Conditions Min. Typ. Max. Units VLPOR 3 VDD supply threshold above which POR out- put is guaranteed to be driven low VDD ramping up 1 — — 1.15 V VHPOR 3 VDD supply threshold above which POR output is guaranteed driven high, and device initializes VDD ramping up 1 — — 2.1 V tDPOR POR delay 2 VDD ramping up to 3.3V in <10µs CREF = 0.1µF —3— ms VRESET VDD supply threshold below which will trigger a reset cycle from the “ON’ state. VDD ramping down 1 1.8 — 2.1 V 1. POR tests run with 10kΩ resistor pulled up to VDD. 2. 1MHz clock must be present. 3. Hysteresis = 50mV. |
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Similar Description - ISPPAC-POWR1208P1 |
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