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ISPPAC-POWR1208P1 Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPPAC-POWR1208P1 Datasheet(HTML) 2 Page - Lattice Semiconductor |
2 / 34 page Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet 3-2 Power Supply Sequence Controller and Monitor The ispPAC-POWR1208P1 device is specifically designed as a fully-programmable power supply sequencing con- troller and monitor for managing up to eight separate power supplies, as well as monitoring up to 12 analog inputs or supplies. The ispPAC-POWR1208P1 device contains an internal PLD that is programmable by the user to imple- ment digital logic functions and control state machines. The internal PLD connects to four programmable timers, special purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either an internal programmable clock oscillator or an external clock source. The voltage monitors are arranged as 12 independent comparators, each with 384 programmable trip-point set- tings ranging from 0.68V to 5.392V in roughly 0.5% steps. An additional low-voltage threshold (80mV) is also pro- vided for sensing power-off conditions. The voltage monitors incorporate two features designed to increase their robustness. The first is a small amount of hysteresis. In general, more hysteresis implies more noise immunity, but as trip-points decrease a fixed amount of hysteresis would adversely affect the trip-point accuracy. For this reason the ispPAC-POWR1208P1’s voltage mon- itors use a scheme in which hysteresis scales with trip-point voltages remaining at a nearly constant 0.5% of the selected trip-point. Hysteresis is 30mV for a 5.932V trip-point and scales down to 4mV for a 0.68V trip-point. The second feature that increases the voltage monitor’s robustness are a synchronizer and digital filter in each monitor circuit. The filter may be optionally enabled to provide higher noise immunity at the cost of a somewhat increased response time. The programmable logic functions consist of a block of 36 inputs with 81 product terms and 16 macrocells. The architecture supports the steering of product terms to enhance the overall usability. Output pins are configurable in two different modes. There are eight outputs for controlling eight different power supplies. OUT5-OUT8 are open-drain outputs for interfacing to other circuits. The HVOUT1-HVOUT4 pins can be programmed individually as open-drain outputs or as high voltage FET gate drivers. As high voltage FET gate driver outputs, they can be used to drive an external N-Channel MOSFET as a switch to control the voltage ramp- up of the target board. The four HVOUT drivers have programmable current and voltage levels. Figure 3-1. ispPAC-POWR1208P1 Block Diagram Sequence Controller CPLD 36 I/P & 16 Macrocell GLB Comparator Outputs High Voltage Outputs Analog Inputs CLKIO Digital Inputs 250kHz Internal OSC 4 Timers Logic Outputs 12 8 4 4 5 COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 COMP7 COMP8 OUT5 OUT6 OUT7 OUT8 HVOUT1 HVOUT2 HVOUT3 HVOUT4 VDD ispPAC-POWR1208P1 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VMON11 VMON12 IN1 RESET IN2 IN3 IN4 |
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