 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ORLI10G-3BM680C Datasheet(PDF) 2 Page - Lattice Semiconductor |
|
||||||||||||||||||||||||||||||
ORLI10G-3BM680C Datasheet(HTML) 2 Page - Lattice Semiconductor |
|
|
2 / 80 page  Lattice Semiconductor ORCA ORLI10G Data Sheet 2 Embedded Function Features • Provides a line-interface to system-interface with various system standards such as OC-192/STM-64 SONET/SDH, quad OC-48/STM-16 10 Gbits/s Ethernet, and 10 Gbits/s OTN (digital wrapper/strong FEC) or 12.5 Gbits/s SuperFEC. • Embedded PLLs with programmable M/N multiplication/division values provide flexible data rate conversion between line side and system side. • Line-side supports 16-bit LVDS data with multiple line frequencies supported up to 850 MHz, depending on sys- tem standard. • Line-side interface, including timing and jitter specifications, compliant to OIF 99.102.5 standard. • Receive-side interface can be split into four separate asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data inter- face for each) with a separate clock for each for transfer to the FPGA logic. • Data and clock rates divided by 4 or 8 for use in FPGA logic. • LVDS I/Os compliant with EIA ®-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow high-speed operation. • Low-power LVDS buffers. Programmable Features • High-performance programmable logic: – 0.16 µm 7-level metal technology. – Internal performance of >250 MHz. – Over 400k usable FPGA system gates. – Meets multiple I/O interface standards. – 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. • Traditional I/O selections: – LVTTL (3.3 V) and LVCMOS (2.5 V, and 1.8 V) I/Os. – Per pin selectable I/O clamping diodes provide 3.3 V PCI compliance. – Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. – Two slew rates supported (fast and slew limited). – Fast-capture input latch and input Flip-Flop latch for reduced input setup time and zero hold time. – Fast open-drain drive capability. – Capability to register 3-state enable signal. – Off-chip clock drive capability. – Two input function generator in output path. • New programmable high-speed I/O: – Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR. – Double-ended: LVDS, bused-LVDS, LVPECL. Programmable (on/off) internal parallel termination (100 Ω) also supported for these I/Os. • New capability to (de)multiplex I/O signals: – New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate). – New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). • Enhanced twin-quad Programmable Function Unit (PFU): – Eight 16-bit Look-Up Tables (LUTs) per PFU. – Nine user registers per PFU, one following each LUT, organized to allow two nibbles to act independently, plus one extra for arithmetic operations. – New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. |
Similar Part No. - ORLI10G-3BM680C |
|
Similar Description - ORLI10G-3BM680C |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
