 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ORSO82G5 Datasheet(PDF) 5 Page - Lattice Semiconductor |
|
||||||||||||||||||||||||||||||
ORSO82G5 Datasheet(HTML) 5 Page - Lattice Semiconductor |
|
|
5 / 153 page  Lattice Semiconductor ORCA ORSO42G5 and ORSO82G5 Data Sheet 5 • Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. • Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. • Supplemental Logic and Interconnect Cell (SLIC) provides eight 3-statable buffers, up to a 10-bit decoder, and PAL™-like AND-OR-Invert (AOI) in each programmable logic cell. • New 200 MHz embedded block-port RAM blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be configured as: – 1—512 x 18 (block-port, two read/two write) with optional built in arbitration. – 1—256 x 36 (dual-port, one read/one write). – 1—1K x 9 (dual-port, one read/one write). – 2—512 x 9 (dual-port, one read/one write for each). – 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). – Supports joining of RAM blocks. – Two 16 x 8-bit Content Addressable Memory (CAM) support. – FIFO 512 x 18, 256 x 36, 1Kx 9, or dual 512 x 9. – Constant multiply (8 x 16 or 16 x 8). – Dual variable multiply (8 x 8). • Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built- in system registers that act as the control and status center for the device. • Built-in testability: – Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG). – Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. – TS_ALL testability function to 3-state all I/O pins. – New temperature-sensing diode. • Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. • New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. • PCI local bus compliant for FPGA I/Os. Programmable Logic System Features • Improved PowerPC ® 860 and PowerPC II high-speed synchronous MicroProcessor Interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. • New embedded system bus facilitates communication among the MicroProcessor Interface, configuration logic, Embedded Block RAM, FPGA logic, and embedded standard cell blocks. • Variable size bused readback of configuration data with the built-in MicroProcessor Interface and system bus. • Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. • New clock routing structures for global and local clocking significantly increases speed and reduces skew. • New local clock routing structures allow creation of localized clock trees. • Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved |
Similar Part No. - ORSO82G5 |
|
Similar Description - ORSO82G5 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
