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ORSO42G5-1BM484I Datasheet(PDF) 1 Page - Lattice Semiconductor |
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ORSO42G5-1BM484I Datasheet(HTML) 1 Page - Lattice Semiconductor |
1 / 153 page www.latticesemi.com 1 DS1028_08.0 ORCA ® ORSO42G5 and ORSO82G5 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs July 2008 Data Sheet DS1028 © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbps and 20 Gbps respectively. These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non- SONET applications. The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6- 2.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces. With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design- ers can build a configurable interface using proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbps backplane data connection and, with the ORSO82G5, support both work and protection connections between a line card and switch fabric. The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network designers will benefit from using the backplane transceiver as a network termination device. Sister devices, the ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet (XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling, streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi- nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices. Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic . Device PFU Rows PFU Columns Total PFUs FPGA Max User I/O LUTs EBR Blocks 2 EBR Bits (K) FPGA System Gates (K) 1 ORSO42G5 36 36 1296 204 10,368 12 111 333-643 ORSO82G5 36 36 1296 372 10,368 12 111 333-643 1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 4 PLLs. 2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic. |
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