 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ORT82G5-1BM680C Datasheet(PDF) 11 Page - Lattice Semiconductor |
|
||||||||||||||||||||||||||||||
ORT82G5-1BM680C Datasheet(HTML) 11 Page - Lattice Semiconductor |
|
|
11 / 119 page  Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet 11 Additional Information Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA devices, or visit the Lattice web site at www.latticesemi.com. ORT42G5/ORT82G5 Overview The ORT42G5 and ORT82G5 FPSCs provide high-speed backplane transceivers combined with FPGA logic. They are based on the 1.5V OR4E04 ORCA FPGA and have 36 x 36 arrays of Programmable Logic Cells (PLCs). The embedded core, which contains the backplane transceivers is attached to the right side of the device and is inte- grated directly into the FPGA array. A top level diagram of the basic chip configuration is shown in Figure 1. Embedded Core Overview The embedded core portions of the ORT42G5 and ORT82G5 contain respectively four or eight Clock and Data Recovery (CDR) macrocells and Serialize/Deserialize (SERDES) blocks and support 8b/10b (IEEE 802.3.2002) encoded serial links. It is intended for high-speed serial backplane data transmission. Figure 1 shows the ORT42G5 and ORT82G5 top level block diagram and the basic data flow. Boundary scan for the ORT42G5/ORT82G5 only includes programmable I/Os and does not include any of the embedded block I/Os. Figure 1. ORT42G5/ORT82G5 Top Level Block Diagram The serial channels can each operate at up to 3.7 Gbps (2.96 Gbps data rate) with a full-duplex synchronous inter- face with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring and contains independent 4k x 36 RAM blocks. Overviews of the various blocks in the embedded core are presented in the following paragraphs. Serializer and Deserializer (SERDES) The SERDES portion of the core contains two transceiver blocks for serial data transmission at a selectable data rate of 0.6 to 3.7 Gbps. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and high-speed CML interfaces to the serial links. The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high- speed (up to 3.7 Gbps) serial data. Based on data transitions, the receiver locks an analog receive PLL for each channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock. The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbps serial data for off- chip communication. The transmitter generates the necessary 3.7 GHz clocks for operation from a lower speed ref- erence clock. SERDES w/ CLOCK/DATA BYTE- WIDE DATA 8b/10b DECODER/ENCODER 4 or 8 FULL- 0.6 Gbps DATA DUPLEX SERIAL CHANNELS TO 3.7 Gbps 0.6 Gbps DATA TO 3.7 Gbps CML I/Os ORCA SERIES 4 FPGA LOGIC STANDARD FPGA I/Os RECOVERY 4:1 MUX/1:4 DEMUX AND MULTI-CHANNEL ALIGNMENT FIFOs |
Similar Part No. - ORT82G5-1BM680C |
|
Similar Description - ORT82G5-1BM680C |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
