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LC5512MC-75F208I Datasheet(PDF) 33 Page - Lattice Semiconductor |
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LC5512MC-75F208I Datasheet(HTML) 33 Page - Lattice Semiconductor |
33 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 33 Registered Delays tS D-Register Setup Time, Global Clock — 0.28 — 0.31 — 0.35 — 0.55 — 0.52 — ns tS_PT D-Register Setup Time, PT Clock — -0.13 — -0.11 — -0.10 — -0.10 — -0.07 — ns tH D-Register Hold Time — 1.90 — 2.56 — 2.50 — 2.40 — 4.00 — ns tCOi Register Clock to OSA Time — — 0.72 — 1.03 — 0.68 — 0.93 — 1.50 ns tCESi Clock Enable Setup Time — 1.07 — 1.20 — 1.33 — 1.33 — 2.00 — ns tCEHi Clock Enable Hold Time — 0.00 — 0.00 — 0.00 — 0.00 — 0.00 — ns tSIR D-Input Register Setup Time, Global Clock — 0.66 — 0.20 — 0.53 — 0.12 — 0.08 — ns tSIR_PT D-Input Register Setup Time, PT Clock — 0.42 — 0.37 — 0.34 — 0.34 — 0.22 — ns tHIR D-Input Register Hold Time, Global Clock — 0.84 — 1.31 — 1.01 — 1.41 — 2.91 — ns tHIR_PT D-Input Register Hold Time, PT Clock — 0.00 — 0.00 — 0.00 — 0.00 — 0.00 — ns Latched Delays tSL Latch Setup Time, Global Clock — 0.18 — 0.00 — 0.00 — 0.00 — 0.00 — ns tSL_PT Latch Setup Time, PT Clock — 0.18 — 0.00 — 0.00 — 0.00 — 0.34 — ns tHL Latch Hold Time — -0.06 — 0.00 — 0.00 — 0.00 — -0.03 — ns tGOi Latch Gate to OSA Time — — 0.07 — 0.08 — 0.08 — 0.08 — 0.13 ns tPDLi Propagation Delay through Latch to OSA Transparent — — 0.52 — 0.58 — 0.65 — 0.65 — 0.97 ns Reset and Set Delays tSRi Asynchronous Reset or Set to OSA Delay — — 0.23 — 0.26 — 0.29 — 0.29 — 0.43 ns tSRR Asynchronous Reset or Set Recovery — — 0.42 — 0.47 — 0.53 — 0.55 — 0.79 ns eXtended Function Routing Delays tROUTEMF Delay through SRP when Implementing Memory Functions — — 2.00 — 2.25 — 2.51 — 2.61 — 3.76 ns ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter Description Base Parameter -4 -45 -5 -52 -75 Units Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. |
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