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STA559BWQS13TR Datasheet(PDF) 4 Page - STMicroelectronics

Part # STA559BWQS13TR
Description  5-V, 2-A, 2.1-channel high-efficiency digital audio system with QSound QHD
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA559BWQS13TR Datasheet(HTML) 4 Page - STMicroelectronics

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Contents
STA559BWQS
4/66
5.5.7
Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.5.8
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6.1
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.6.2
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6.3
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.4
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.5
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.6
IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6.7
External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.7
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 42
5.7.1
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.7.2
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.7.3
Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.7.4
Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.7.5
Channel 3/line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8
Auto mode registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . . . 44
5.8.1
AutoMode register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.8.2
AutoMode register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.8.3
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.8.4
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.9
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 46
5.9.1
Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.9.2
EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.9.3
Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.9.4
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.9.5
Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.9.6
Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.10
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.10.1
Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.11
Dynamics control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 48
5.11.1
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.11.2
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.11.3
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.11.4
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.12
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 51


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