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LFE26E-7FN256C Datasheet(PDF) 8 Page - Lattice Semiconductor |
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LFE26E-7FN256C Datasheet(HTML) 8 Page - Lattice Semiconductor |
8 / 386 page 2-5 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func- tions can be implemented by each slice: • Addition 2-bit • Subtraction 2-bit • Add/Subtract 2-bit using dynamic control • Up counter 2-bit • Down counter 2-bit • Up/Down counter with Async clear • Up/Down counter with preload (sync) • Ripple mode multiplier building block • Multiplier support • Comparator functions of A and B inputs – A greater-than-or-equal-to B – A not-equal-to B – A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con- figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener- ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit pseudo dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required to Implement Distributed RAM SPR 16X4 PDPR 16X4 Number of slices 3 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM |
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