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LFX1200EC-4F900C Datasheet(PDF) 6 Page - Lattice Semiconductor |
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LFX1200EC-4F900C Datasheet(HTML) 6 Page - Lattice Semiconductor |
6 / 115 page Lattice Semiconductor ispXPGA Family Data Sheet 6 Configurable Logic Element The CLE is made up of a four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder, and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of the AND gate to one of the inputs of the CCG. Of the five inputs that feed each CLE, two are dedicated inputs into each LUT-4 and the remaining three take on varying functionality. The third and fourth inputs can be used as either inputs to the LUT-4 or as a Feed-Thru to the CSE via the WLG. The fifth input can be a data port when the LUT is configured as Distributed Memory, a select line for multiplexer operation, or a Feed-Thru directly to the CSE via the WLG (Figure 2). Look-Up Table – Combinatorial Mode In combinatorial mode, the LUT-4 can implement any logic function up to four inputs. By using the carry chain and the WLG, each LUT-4 can be combined to form the enhanced functions listed in Table 3. Look-Up Table – Distributed Memory Mode In the distributed memory mode, the LUT functions as a memory element. The inputs to the LUT function as Address and Data. Each PFU is capable of implementing up to 64 SRAM bits. Both single and double port RAM can be performed in the PFU (Table 3). Furthermore, the distributed memory can be configured as either synchro- nous or asynchronous memory. Figure 3 illustrates the LUT while in distributed memory mode. When using any LUT in the PFU in memory mode, the Set/Reset signal will be used for Write Enable (WE(SR)) and the CLK0 signal will be used as the clock for synchronous read and write. Figure 3. LUT in Distributed Memory Mode Look-Up Table – Shift Register Mode In the shift register mode, the LUT functions as a 1-bit to 8-bit shift register. This means that each PFU can imple- ment up to four 8-bit shift registers or any cascaded combination. Figure 4 illustrates the LUT when configured in shift register mode. LUT-4 ADDR[0] (IN0) PFUCLK0 ADDR[1] (IN1) ADDR[2] (IN2) ADDR[3] (IN3) CEB0 WE (SR) DOUT (4A) DIN (SEL) |
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