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LM3S600-IRN50-A2T Datasheet(PDF) 11 Page - Bookham, Inc. |
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LM3S600-IRN50-A2T Datasheet(HTML) 11 Page - Bookham, Inc. |
11 / 378 page List of Registers System Control .............................................................................................................................. 48 Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 57 Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................... 59 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 60 Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 61 Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 62 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 64 Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 65 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 66 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 70 Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 71 Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................. 72 Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................... 73 Register 13: Device Identification 1 (DID1), offset 0x004 ....................................................................... 74 Register 14: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 76 Register 15: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 77 Register 16: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 79 Register 17: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 81 Register 18: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 83 Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 84 Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 85 Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 86 Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 87 Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 89 Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 91 Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 93 Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 95 Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ......................... 97 Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................... 99 Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 100 Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 102 Internal Memory ........................................................................................................................... 103 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 109 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 110 Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 111 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 113 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 114 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 115 Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 116 Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 117 Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 118 General-Purpose Input/Outputs (GPIOs) ................................................................................... 119 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 126 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 127 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 128 11 October 01, 2007 Preliminary LM3S600 Microcontroller |
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