UCC1895

UCC2895

UCC3895

SLUS157L − DECEMBER 1999 − REVISED APRIL 2008

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DETAILED PIN DESCRIPTION (continued)

Soft-Start/Disable (SS/DISB)

This pin combines two independent functions.

Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,

externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF

being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal

MOSFET switch.

If an overcurrent fault is sensed (CS = 2.5 V), a soft-stop is initiated. In this mode, SS/DISB sinks a constant

current of (10

detected, all outputs are forced to ground immediately.

Soft-start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and/or

SS/DISB falls below 0.5 V during a soft-stop, SS/DISB switches to a soft-start mode. The pin then sources

constant.

NOTE: SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin voltage

during both soft-start, soft-stop, and disable conditions.

Oscillator Synchronization (SYNC)

This pin is bidirectional (refer to Figure 1). When used as an output, SYNC can be used as a clock, which is the

same as the device’s internal clock. When used as an input, SYNC overrides the chip’s internal oscillator and

act as it’s clock signal. This bidirectional feature allows synchronization of multiple power supplies. Also, the

The internal SYNC circuitry is level sensitive, with an input-low threshold of 1.9 V, and an input-high threshold

of 2.1 V. A resistor as small as 3.9 k

Ω may be tied between SYNC and GND to reduce the sync pulse width.

Chip Supply (VDD)

This is the input pin to the chip. VDD must be bypassed with a minimum of 1.0

µF low ESR, low ESL capacitor

µF low ESR, low ESL between VDD and PGND is recommended.