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LCMXO2280LUTSE-4FTN324CES Datasheet(PDF) 10 Page - Lattice Semiconductor |
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LCMXO2280LUTSE-4FTN324CES Datasheet(HTML) 10 Page - Lattice Semiconductor |
10 / 95 page 2-7 Architecture Lattice Semiconductor MachXO Family Data Sheet The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock/Control Distribution Network The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL out- puts. Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices Routing Clock Pads Primary Clock 0 Primary Clock 1 Primary Clock 2 Primary Clock 3 4 12 16:1 16:1 16:1 16:1 |
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