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LC5512MC-75F208C Datasheet(PDF) 30 Page - Lattice Semiconductor |
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LC5512MC-75F208C Datasheet(HTML) 30 Page - Lattice Semiconductor |
30 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 30 fMAX (RAM) 5 Clock Frequency to RAM in: Single Port Mode — 155 — 155 — 155 — 155 — 93 MHz Dual Port Mode — 155 — 155 — 155 — 155 — 93 MHz Pseudo Dual Port Mode — 180 — 180 — 160 — 160 — 106 MHz fMAX (FIFO) 5 Clock Frequency to FIFO — 225 — 220 — 210 — 210 — 132 MHz tPWR_ON Power-on Time — 200 — 200 — 200 — 200 — 200 µs Timing v.1.8 1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards. 2. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching. 3. Pulse widths and clock widths less than minimum will cause unknown behavior. 4. Standard 16-bit counter using GRP feedback. 5. CAM, FIFO, RAM fMAX specification used shared PT Clk. ispXPLD 5000MX Family External Switching Characteristics (Continued) 1, 2, 3 Over Recommended Operating Conditions Parameter Description -4 -45 -5 -52 -75 Units Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. |
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