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LC5512MC-75Q208C Datasheet(PDF) 15 Page - Lattice Semiconductor |
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LC5512MC-75Q208C Datasheet(HTML) 15 Page - Lattice Semiconductor |
15 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 15 Clock Distribution The ispXPLD 5000MX family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are directly related to the dedicated clock pins (see Secondary Clock Divider exception when using the sysCLOCK cir- cuit). These feed the registers in the MFBs. Note at each register there is the option of inverting the clock if required. Figure 14 shows the clock distribution network. Figure 14. Clock Distribution Network sysCLOCK PLL The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener- ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are de- skewed either at the board level or the device level. The ispXPLD 5000MX devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3 (CLK 2 when using the secondary clock). The optional outputs CLK_OUT can be routed to an I/O pin. The optional PLL_LOCK output is routed into the GRP. The optional input PLL_RST can be routed either from the GRP or directly from an I/O pin. The optional PLL_FBK into can be routed directly from a pin. Figure 15 shows the ispXPLD 5000MX PLL block diagram. Figure 16 shows the connection of optional inputs and outputs. sysCLOCK PLLs Global Clock Routing Clock Net PLL0 CLK_OUT0 SEC_OUT0 VREF0 CLK0 CLK1 GCLK0 GCLK1 I/O/CLK_OUT0 Clock Net Clock Net PLL1 CLK_OUT1 SEC_OUT1 CLK3 CLK2 GCLK3 GCLK2 I/O/CLK_OUT1 Clock Net To Macrocells To Macrocells To Macrocells To Macrocells VREF1 VREF3 VREF2 |
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