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BQ20Z75DBT-V160 Datasheet(PDF) 7 Page - Texas Instruments |
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BQ20Z75DBT-V160 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 18 page bq20z75 www.ti.com............................................................................................................................................................... SLUS723C – JULY 2007 – REVISED JULY 2008 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, VREG25 = 2.41 V to 2.59 V, VBAT = 14V, CREG25 = 1µF, CREG33 = 2.2µF; typical values at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVCELL+OU VC(n) – VC(n+1) = 0V; VCELL+ = Drive Current to VCELL+ capacitor 12 18 µA T 0V; TA = –40°C to 100°C CELL output (VC2 = VC1 = 18V) – VVCELL+O CELL offset error –18 –1 18 mV CELL output (VC2 = VC1 = 0V) IVCnL VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3V –1 0.01 1 µA CELL BALANCING RDS(on) for internal FET switch at VDS RBAL internal cell balancing FET resistance 200 400 600 Ω = 2V; TA = 25°C HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted) VOL = 25mV (min) 15 25 35 V(OL) OL detection threshold voltage accuracy VOL = 100mV; RSNS = 0, 1 90 100 110 mV VOL = 205mV (max) 185 205 225 VSCC = 50mV (min) 30 50 70 SCC detection threshold voltage V(SCC) VSCC = 200mV; RSNS = 0, 1 180 200 220 mV accuracy VSCC = 475mV (max) 428 475 523 VSCD = –50mV (min) –30 –50 –70 SCD detection threshold voltage V(SCD) VSCD = –200mV; RSNS = 0, 1 –180 –200 –220 mV accuracy VSCD = –475mV (max) –428 –475 –523 tda Delay time accuracy ±15.25 µs tpd Protection circuit propagation delay 50 µs FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted) VDSGON = VDSG – VPACK; VGS = VDSGON DSG pin output on voltage 10M Ω;DSG and CHG on; TA = 8 12 16 V –40°C to 100°C VCHGON = VCHG – VBAT; VGS = VCHGON CHG pin output on voltage 10M Ω;DSG and CHG on; TA = 8 12 16 V –40°C to 100°C VDSGOFF DSG pin output off voltage VDSGOFF = VDSG – VPACK 0.2 V VCHGOFF CHG pin output off voltage VCHGOFF = VCHG – VBAT 0.2 V CL=4700pF; VPACK ≤ DSG ≤VPACK + 400 1000 4V tR Rise time µs CL=4700pF; VBAT ≤ CHG ≤VBAT + 4V 400 1000 CL=4700pF; VPACK + VDSGON ≤ DSG 40 200 ≤VPACK + 1V tF Fall time µs CL=4700pF; VBAT + VCHGON ≤ CHG 40 200 ≤VBAT + 1V VZVCHG ZVCHG clamp voltage BAT = 4.5V 3.3 3.5 3.7 V LOGIC; TA = –40°C to 100°C (unless otherwise noted) ALERT 60 100 200 RPULLUP Internal pullup resistance k Ω RESET 1 3 6 ALERT 0.2 RESET; VBAT = 7V; VREG25 = 1.5V; VOL Logic low output voltage level 0.4 V IRESET = 200µA GPOD; IGPOD = 50µA 0.6 LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): bq20z75 |
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