LC5512MC-52Q484C datasheet(18/92 Pages) LATTICE

Part #	LC5512MC-52Q484C

Description	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family

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Manufacturer	LATTICE [Lattice Semiconductor]

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Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

18

Figure 17. I/O Cell

Table 10. Shared PTOE Segments

sysIO Standards

Each I/O within a bank is individually conﬁgurable based on the VCCO and VREF settings. Some standards also

require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for

VCCO, VREF and VTT. For more information on the sysIO capability, please refer to Lattice technical note number

TN1000, sysIO Usage Guidelines for Lattice Devices, available at www.latticesemi.com.

Table 11. Number of I/Os per Bank

Device

MFBs Associated With Segments

ispXPLD 5256MX

(A, B, C, D) (E, F, G, H)

ispXPLD 5512MX

(A, B, C, D) (E, F, G, H)

(I, J, K, L) (M, N, O, P)

ispXPLD 5768MX

(A, B, C, D) (E, F, G, H)

(I, J, K, L) (M, N, O, P)

(Q, R, S, T) (U, V, W, Z)

ispXPLD 51024MX

(A, B, C, D) (E, F, G, H)

(I, J, K, L) (M, N, O, P)

(Q, R, S, T) (U, V, W, Z)

(Y, Z, AA, AB) (AC, AD, AE, AF)

Device

Maximum Number of I/Os per Bank (n)

ispXPLD 5256MX

36

ispXPLD 5512MX

68

ispXPLD 5768MX

96

ispXPLD 51024MX

96

Shared PTOE 0

Shared PTOE 1

Shared PTOE 2

Shared PTOE 3

PTOE

GOE0

GOE1

TOE

VCCO to All

Other I/Os

in Bank

VCCO for

this Bank

Differential

I/O Buffer

To Primary

Macrocell

To Alternate

Macrocell

Delay Element

To Adjacent

I/O Pad

VREF Dependent

Input Buff

VREF to All

other I/Os in Bank

er

CMOS/TTL

Input Buffer

(VREF Independent)

I/O

Pad

GND

Data Output from

Primary Macrocell

Data Output from

Alternate Macrocells

Output Sharing

Array (OSA)

Data Input to Routing

To Adjacent I/O Pad

Differential

Output Buffer

(VCCO Independent

for Open Drain

Outputs)

+

–

+

–

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LC5512MC-52Q484C Datasheet(PDF) 18 Page - Lattice Semiconductor

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