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LC5512MV-45F672C Datasheet(PDF) 10 Page - Lattice Semiconductor

Part No. LC5512MV-45F672C
Description  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
10
True Dual-Port SRAM Mode
In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent
read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the
MFB. Figure 9 shows the block diagram of the dual port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same
clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and
reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5
shows the possible sources for the clock, clock enable and initialization signals for the various registers.
Figure 9. Dual-Port SRAM Block Diagram
Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode
Register
Input
Source
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock
CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected sig-
nal can be inverted if desired.
Clock Enable
CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected sig-
nal can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RSTA (RSTB).
RSTA (RSTB) can be inverted is desired.
Read/Write Address
(ADA[0:8-12])
Clock A (CLKA)
Write/Read A (WRA)
Reset A (RSTA)
68 Inputs
From
Routing
Dual
Port
SRAM
Array
PORT A
PORT B
Similar signals
as PORT A:
ADB[0:8-12], RSTB,
CLKB, CENB, WRB,
CSB[0,1], DIB[0:0,1,3,7,15]
Write Data
(DIA[0:0,1,3,7,15])
Chip Sel A (CSA [0:1])
Clk En A (CENA)
RESET
CLK0
CLK3
CLK1
CLK2
RD Data A
(DOA[0:0-15])
RD Data B
(DOB[0:0-15])




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