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LC5512MC-5F672C Datasheet(PDF) 39 Page - Lattice Semiconductor |
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LC5512MC-5F672C Datasheet(HTML) 39 Page - Lattice Semiconductor |
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39 / 92 page  Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 39 tDPCEBS Clock Enable B Setup before Clock B Time — 2.33 — 2.33 — 2.33 — 2.33 — 3.03 — ns tDPCEBH Clock Enable Hold B after Clock B Time — -2.95 — -2.95 — -2.95 — -2.95 — -2.27 — ns tDPADDBS Address B Setup before Clock B Time — -0.27 — -0.27 — -0.27 — -0.27 — -0.21 — ns tDPADDBH Address B Hold time after Clock B Time — -0.01 — -0.01 — -0.01 — -0.01 — -0.01 — ns tDPRWBS R/W B Setup before Clock B Time — -0.27 — -0.27 — -0.27 — -0.27 — -0.21 — ns tDPRWBH R/W B Hold time after Clock B Time — -0.01 — -0.01 — -0.01 — -0.01 — -0.01 — ns tDPDATABS Write Data B Setup before Clock B Time — -0.27 — -0.27 — -0.27 — -0.27 — -0.21 — ns tDPDATABH Write Data B Hold after Clock B Time — -0.01 — -0.01 — -0.01 — -0.01 — -0.01 — ns tDPRCLKAO Read Clock A to Output Delay — — 5.97 — 5.92 — 5.86 — 5.65 — 9.86 ns tDPRCLKBO Read Clock B to Output Delay — — 5.16 — 5.16 — 5.16 — 5.16 — 6.71 ns tDPCLKSKEW Opposite Clock Cycle Delay — 1.40 — 1.40 — 1.40 — 1.40 — 1.83 — ns tDPRSTO Reset to RAM Output Delay — — 3.30 — 3.30 — 3.30 — 3.30 — 4.29 ns tDPRSTR Reset Recovery Time — 1.20 — 1.20 — 1.20 — 1.20 — 1.56 — ns tDPRSTPW Reset Pulse Width — 0.14 — 0.14 — 0.14 — 0.14 — 0.19 — ns Timing v.1.8 1. The PT-delay to clock of RAM/FIFO/CAM should be tBCLK instead of tPTCLK. 2. The PT-delay to set/reset of RAM/FIFO/CAM should be tBSR instead of tPTSR. ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Over Recommended Operating Conditions Parameter Description Base Parameter -4 -45 -5 -52 -75 Units Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. |
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