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LC5512MC-5FN672C Datasheet(PDF) 31 Page - Lattice Semiconductor |
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LC5512MC-5FN672C Datasheet(HTML) 31 Page - Lattice Semiconductor |
31 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 31 Timing Model The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in Figure 20 shows the specific delay paths. Once the implementation of a given function is determined either con- ceptually or from the software report file, the delay path of a function can easily be determined from the timing model. The Lattice design tools report the timing delays based on the same timing model. Note that internal timing parameters are for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device. Figure 20. ispXPLD 5000MX Timing Model Diagram MC Reg. t BUF t IOO t EN t DIS OUT DATA C.E. S/R Q Feedback t PTCLK t BCLK IN t GCLK _IN t IOI GCLK From Feedback RST OE t INREG t INDIO Memory Functions t PDi t PTSR t BSR t OSA t PTOE t SPTOE t GPTOE t IN t IOI t GOE t IOI t RST t IOI t PDb CLK, CE and Reset Only 3 t PLL _DELAY t PLL _SEC_DELAY t SUM t CICOMFB tCICOMC t EXP t PTSA t FBK CASC t ROUTE t t BLA Some paths not available in memory mode. Refer to timing tables for details. Path only available for FIFO Flags tROUTEMF tGCLK |
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