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V827332N04S Datasheet(PDF) 6 Page - Mosel Vitelic, Corp |
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V827332N04S Datasheet(HTML) 6 Page - Mosel Vitelic, Corp |
6 / 15 page 6 MOSEL VITELIC V827332N04S V827332N04S Rev. 1.1 May 2002 29 Minimum RAS to CAS delay(=tRCD) 20ns 20ns 18ns 50h 50h 48h 30 Minimum active to precharge time(=tRAS) 50ns 45ns 45ns 32h 2Dh 2Dh 31 Module Row density 256MB 40h 32 Command and address signal input setup time 1.1ns 0.9ns 0.9ns B0h 90h 90h 33 Command and address signal input hold time 1.1ns 0.9ns 0.9ns B0h 90h 90h 34 Data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h 35 Data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h 36-40 Superset information (may be used in future) - 00h 41 SDRAM device minimum active to active/auto-refresh time (=tRC) 70ns 65ns 60ns 46h 41h 3Ch 42 SDRAM device minimum active to autorefresh to active/auto-refresh time (=tRFC) 80ns 75ns 67ns 50h 4Bh 43h 43 SDRAM device maximum device cycle time (=tCK MAX) 12ns 12ns 12ns 30h 30h 30h 44 SDRAM device maximum skew between DQS and DQ signals (=tDQSQ) 0.6ns 0.5ns 0.5ns 3Ch 32h 32h 45 SDRAM device maximum read datahold skew factor (=tQHS) 1ns 0.75ns 0.75ns A0h 75h 75h 62 SPD data revision code Initial release 00h 63 Checksum for Bytes 0 ~ 62 - F5 3B DA 64 Manufacturer JEDEC ID code Mosel Vitelic 40h 65 -71 ....... Manufacturer JEDEC ID code 00h 72 Manufacturing location 02=Taiwan 05=China 0A=S-CH 73-90 Module part number (ASCII) V827332N04S 91 Manufacturer revison code (For PCB) 0 00 92 Manufacturer revison code (For component) 0 00 93 Manufacturing date (Week) - - 94 Manufacturing date (Year) - - 95~98 Assembly serial # - - 99~127 Manufacturer specific data (may be used in future) Undefined 00h 128~255 Open for customer use Undefined 00h Byte # Function described Function Supported Hex value A1 B0 B1 A1 B0 B1 Serial Presence Detect Information (cont.) |
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