M95640DW3TG datasheet(10/46 Pages) STMICROELECTRONICS

Part #	M95640DW3TG

Description	32 Kbit and 64 Kbit serial SPI bus EEPROMs with high-speed clock

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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10 / 46 page

Connecting to the SPI bus

M95320, M95640, M95320-x, M95640-x

10/46

3

Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such

as the Read from Memory Array and Read Status Register instructions) have been clocked

into the device.

Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is

selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the

others being high impedance.

Figure 3.

Bus master and memory devices on the SPI bus

1.

The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

The pull-up resistor R (represented in Figure 3) ensures that a device is not selected if the

bus master leaves the S line in the high impedance state.

In applications where the bus master might enter a state where all inputs/outputs SPI bus

would be in high impedance at the same time (for example, if the bus master is reset during

the transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S line is pulled high): this will ensure that S and C do not become high at the

same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

AI12836b

SPI bus master

SPI memory

device

SDO

SDI

SCK

CQD

S

SPI memory

device

CQD

S

SPI memory

device

CQD

S

CS3

CS2

CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

W

HOLD

W

HOLD

W

HOLD

RR

R

VCC

VSS

R

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M95640DW3TG Datasheet(PDF) 10 Page - STMicroelectronics

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