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MCF54455 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

Part # MCF54455
Description  ColdFire짰 Microprocessor
Download  48 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCF54455 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc

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Pin Assignments and Reset States
MCF5445x ColdFire® Microprocessor Data Sheet, Rev. 2
Freescale Semiconductor
7
3.3.1
Power-Up Sequence
If EVDD/SDVDD are powered up with the IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected
to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD
must power up. The rise times on the power supplies should be slower than 50 V/millisecond to avoid turning on the internal
ESD protection clamp diodes.
3.3.2
Power-Down Sequence
If IVDD/PVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PVDD power down before EVDD or SDVDD must power down. There are no
requirements for the fall times of the power supplies.
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF5445x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed discussion
of the MCF5445x signals, consult the MCF54455 Reference Manual (MCF54455RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., FB_AD23), while designations for multiple signals within a
group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO default to their GPIO functionality. See Table 3 for a list of the
exceptions.
Table 3. Special-Case Default Signal Functionality
Pin
256 MAPBGA
360 TEPBGA
FB_AD[31:0]
FB_AD[31:0] except when serial boot selects 0-bit
boot port size.
FB_BE/BWE[3:0]
FB_BE/BWE[3:0]
FB_CS[3:1]
FB_CS[3:1]
FB_OE
FB_OE
FB_R/W
FB_R/W
FB_TA
FB_TA
FB_TS
FB_TS


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