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HD49340NP Datasheet(PDF) 2 Page - Renesas Technology Corp |
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HD49340NP Datasheet(HTML) 2 Page - Renesas Technology Corp |
2 / 22 page HD49340NP/HNP Rev.1.0 Apr 20, 2004 page 2 of 21 Pin Arrangement 27 26 25 24 23 22 21 20 19 123456789 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 (Top view) AVSS SPSIG SPBLK OBP PBLK DVDD ADCLK DVSS DRDVDD VRM VRT VRB DVDD DVSS CS SDATA SCK D0 Pin Description Pin No. Symbol Description I/O Analog(A) or Digital(D) 1 to 9 D0 to D9 Digital output O D 10 DRDVDD Output buffer power supply (3 V) — D 11 DVSS Digital ground (0 V) — D 12 ADCLK ADC conversion clock input pin I D 13 DVDD Digital power supply (3 V) — D 14 PBLK Preblanking input pin I D 15 OBP Optical black pulse input pin I D 16 SPBLK Black level sampling clock input pin I D 17 SPSIG Signal level sampling clock input pin I D 18 AVSS Analog ground (0 V) — A 19 AVDD Analog power supply (3 V) — A 20 BLKSH Black level S/H pin — A 21 BLKFB Black level FB pin — A 22 CDSIN CDS input pin I A 23 BLKC Black level C pin — A 24 BIAS Internal bias pin Connect a 33 k Ω resistor between BIAS and AV SS. — A 25 AVDD Analog power supply (3 V) — A 26 AVSS Analog ground (0 V) — A 27 ADCIN ADC input pin — A 28 VRM Reference voltage pin 1 Connect a 0.1 µF ceramic capacitor between VRM and AV SS. — A 29 VRT Reference voltage pin 3 Connect a 0.1 µF ceramic capacitor between VRT and AV SS. — A 30 VRB Reference voltage pin 2 Connect a 0.1 µF ceramic capacitor between VRB and AV SS. — A |
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