HD74LV166A

Rev.3.00 Jun. 04, 2004 page 2 of 9

Function Table

Inputs

Internal outputs

Output

CLR

SH/

LD

CLK INH

CLK

SER

A ... H

QA

QB

QH

LX

X

X

X

X

LLL

H

X

LLX

X

HL

L

↑

X

a ... h

a

b

h

HHL

↑

HX

HHL

↑

LX

HX

H

↑

XX

Note:

H: High level

L: Low level

↑: Low to high transition

X: Immaterial

a ... h: Parallel data

Outputs remain unchanged.

Data shifted from the previous stage on a positive edge at the clock input.

Pin Arrangement

13

14

11

12

15

16

9

10

SH/

LD

H

QH

G

F

1

2

3

4

5

6

7

8

SER

A

B

C

D

CLK INH

CLK

GND

E

CLR

(Top view)