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HD74LVC373A Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74LVC373A Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 9 page Rev.4.00 Jul. 27, 2004 page 1 of 8 HD74LVC373A Octal D-type Transparent Latches with 3-state Outputs REJ03D0354–0400Z (Previous ADE-205-112B (Z)) Rev.4.00 Jul. 27, 2004 Description The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • V CC = 2.0 V to 5.5 V • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs V OUT (Max.) = 5.5 V (@VCC = 0 V or output off state) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@V CC = 3.0 V to 5.5 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LVC373AFPEL SOP–20 pin (JEITA) FP–20DAV FP EL (2,000 pcs/reel) HD74LVC373ATELL TSSOP–20 pin TTP–20DAV T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs G LE D Output Q HX X Z LH L L LH H H LL X Q0 H: High level L: Low level X: Immaterial Z: High impedance Q0: Level of Q before the indicated steady input conditions were established. |
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